1. Field of the Invention
The present invention relates to a logic simulator for semiconductor integrated circuit devices.
2. Description of the Background Art
FIG. 14 is a circuit diagram of an exemplary logic circuit to be logic-simulated by a logic simulator.
Referring to FIG. 14, an input signal SI is applied to a first input of an AND gate 31. A second input of the AND gate 31 receives the output of an exclusive-OR gate 30, and the output of the AND gate 31 is applied to a D-input of a DFF (D flip-flop) 33.
The DFF 33 has a clock input receiving a clock signal CLK and outputs a Q-output Q1 to the outside. The Q-output Q1 is also applied to first inputs of the exclusive OR gate 30 and an exclusive-NOR gate 32. A DFF 34 has a clock input receiving the clock signal CLK and a D-input receiving the output of the exclusive-NOR gate 32 and outputs a Q-output Q0 to the outside. The Q-output Q0 is also applied to second inputs of the exclusive-OR gate 30 and exclusive-NOR gate 32 in common. A reset signal RST is applied to reset inputs R of the DFFs 33 and 34.
The circuit to be simulated constructed as described above has the property of providing, when the input signal SI is set to "H", the Q-output Q1 of "H" and the Q-output Q0 of "L" after input of two pulses of the clock signal CLK independently of the initial value of the Q-outputs Q1 and Q10 of the DFFs 33 and 34.
In logic simulation by the conventional logic simulator, the output constantly has an indefinite value X where the input signal has the indefinite value X. Thus, when the logic circuit as above constructed is to be simulated wherein the D-input of the DFF 33 or the DFF 34 is indefinite X, the Q-output Q1 or the Q-output Q0 remains indefinite X. That is, the signal which has a definite value in practical operation is indefinite in logic simulation.
To overcome such a shortcoming, the conventional logic simulator comprises definite value setting means for forcing the DFF 33 or DFF 34 to return to a definite value by the reset signal RST for logic simulation independently of the necessity thereof in the practical circuit.
The conventional logic simulator is disadvantageous in that the circuit to be simulated, once having outputted an indefinite value, keeps outputting the indefinite value in logic simulation although the circuit surely outputs a definite value after a predetermined period has elapsed since it outputted the indefinite value in practical operation.
For a solution of the problem, it is necessary to additionally provide the definite value setting means for forcing the output of the logic circuit to return to a definite value such as the reset circuit, as above mentioned.
The result is the production of the definite value setting means that is required only in logic simulation in the fabrication of the circuit to be simulated as a practical logic circuit. This results in an increased circuit scale and a cumbersome step of applying an external signal for controlling the added definite value setting means, leading to a reduction in degree of integration and efficiency of the logic circuit to be practically fabricated.